1. Field of the Invention
Embodiments of the invention relate to switching power supply devices.
2. Description of the Related Art
To secure stability and safety of a commercial power system, a switching power supply device which consumes power higher than 75 W is typically obligated to make power factor correction. Therefore, there has been recently proposed a switching power supply device equipped with a small-sized and highly efficient power factor correction converter (PFC) and a DC-DC converter which converts a DC voltage obtained from the power factor correction converter into a DC output voltage in accordance with specifications of a load (see, for example, Japanese patent publication no. JP-A-2007-288855). A quasi-resonant converter (QR) low in load imposed on a secondary-side rectifier diode is often used as this type DC-DC converter when the rated load is about 100 W.
FIG. 6 is a diagram of schematic configuration of a switching power supply device 1 equipped with a power factor correction converter 2 and a DC-DC converter (quasi-resonant converter) 3. In FIG. 6, the reference numeral 4 designates a rectifier circuit which rectifies AC power fed from a commercial power supply 5 and inputs the rectified AC power to the power factor correction converter 2, and the reference numeral 6 designates a noise filter which is interposed between the rectifier circuit 4 and the commercial power supply 5.
The power factor correction converter 2 schematically has an inductor L1 which is connected to the rectifier circuit 4, a switching element Q1 which forms a current path through the inductor L1 between the switching element Q1 and the rectifier circuit 4 when the switching element Q1 is on, and a diode D1 which forms a current path between the inductor L1 and an output capacitor C2 when the switching element Q1 is off. A control circuit IC1 controls a current flowing in the inductor L1 by driving the switching element Q1 on/off to thereby obtain a stabilized DC voltage Vb.
The reference signs R1 and R2 designate resistors which divide and detect the DC voltage Vb obtained by the output capacitor C2 and feed the detected DC voltage Vb back to the control circuit IC1. The reference sign R3 designates a shunt resistor for detecting a current (load current) flowing through the switching power supply device 1. Operation of the thus configured power factor correction converter 2 and effects and functions thereof have been introduced in detail, as in, for example, Japanese patent publication no. JP-A-2010-220330 etc.
The DC-DC converter (quasi-resonant converter) 3 schematically has a switching element Q2 which is connected in series with a primary winding P1 of an isolation transformer T to which the output (DC voltage Vb) of the power factor correction converter 2 is applied, a resonant capacitor C4 which is provided in parallel with the switching element Q2, and an output capacitor C5 which is connected to a secondary winding S1 of the isolation transformer T through a rectifier diode D2. A control circuit IC2 generates quasi-resonance between leakage inductance of the isolation transformer T and the resonant capacitor C4 by driving the switching element Q2 on/off to thereby generate a predetermined DC output voltage Vo.
The reference signs R5 and R6 designate resistors which divide and detect a DC output voltage Vo obtained by the output capacitor C5 and feed the detected DC output voltage Vo back to the control circuit IC2 through a feedback circuit FB. The reference sign R4 designates a shunt resistor for detecting a current flowing in the switching element Q2. The DC-DC converter 3 is configured to detect a ZCD voltage generated at an auxiliary winding P2 of the isolation transformer T to thereby control turn-on timing of the switching element Q2. Operation of the thus configured DC-DC converter (quasi-resonant converter) 3 and effects and functions thereof have been introduced in detail, as in, for example, Japanese patent publication no. JP-A-2011-15570 etc.
Incidentally, a load state detecting circuit 7 which detects a load state and outputs an operation-enable signal EN for the power factor correction converter 2 to enable or stop operation of the power factor correction converter 2 is provided in the DC-DC converter 3. An operation control circuit 8 which enables or stops operation of the power factor correction converter 2 in accordance with the operation-enable signal EN is provided in the power factor correction converter 2. The load state detecting circuit 7 eliminates the loss in the power factor correction converter 2 by stopping operation (working) of the power factor correction converter 2, for example, at a light load state in which the input electric power is lower than 75 W. In this manner, the load state detecting circuit 7 plays a role of improving the conversion efficiency of the power factor correction converter 2.
Such a load state detecting circuit 7 is configured, for example, as shown in FIG. 7 and is embedded in the control circuit IC2. The load state detecting circuit 7 has a comparator (light load detecting circuit) 7b which sets a flip-flop 7a by determining that the state is a light load state when the feedback voltage FB used for the on/off control of the switching element Q2 in the DC-DC converter 3 is lower than a preset first threshold voltage Vref1, and a comparator (normal load detecting circuit) 7c which resets the flip-flop 7a by determining that the state is a normal load state when the feedback voltage FB is larger than a second threshold voltage Vref2 (>Vref1) which will be described later. The output of the flip-flop 7a is delayed by means of a delay circuit 7d using charging/discharging of a capacitor Ct to make control to set/reset a flip-flop 7e. Thus, the operation-enable signal EN is obtained as a set output of the flip-flop 7e. 
The delay circuit 7d has the capacitor Ct charged by a constant current source It, and a switching element S which is provided in parallel with the capacitor Ct. When the output of the flip-flop 7a is [H], the switching element S is operated to be off (shut off) so that the capacitor Ct is charged. When the output of the flip-flop 7a is [L], the switching element S is operated to be on (conductive) so that electric charge stored in the capacitor Ct is discharged through a resistor Rt. The delay circuit 7d further has a comparator 7f which resets the flip-flop 7e when a charged voltage Vd of the capacitor Ct is higher than a reference voltage Vth2, and a comparator 7g which sets the flip-flop 7e when the charged voltage Vd is lower than a reference voltage Vth1.
Operation of the load state detecting circuit 7 configured thus will be described briefly as follows. When a load Po becomes light so that the feedback voltage FB decreases accordingly to be lower than the first threshold voltage Vref1 as in a waveform diagram of the operation of the load state detecting circuit 7 shown in FIG. 8, the flip-flop 7a is set. Then, the switching element S of the delay circuit 7d is turned off due to the setting of the flip-flop 7a so that the capacitor Ct is charged with charging characteristic determined based on the capacitance of the capacitor Ct and a constant current fed from the constant current source It. When the charged voltage Vd of the capacitor Ct is higher than the reference voltage Vth2 after the passage of a predetermined time Td-off, the flip-flop 7e is reset so that the operation-enable signal EN turns to [L] to thereby make control to stop the operation of the power factor correction converter 2.
When the operation (working) of the power factor correction converter 2 is stopped in this manner, the output voltage Vb of the power factor correction converter 2 is reduced gradually and then settled down to a voltage determined based on an AC voltage Vac applied from the commercial power supply 5. The output voltage Vb of the power factor correction converter 2 on this occasion changes periodically in a cycle based on rectification of the AC voltage Vac and with a change width determined based on the size of the load Po and the capacitance of the output capacitor C1.
When the load Po becomes heavy in a state where operation of the power factor correction converter 2 is stopped, the feedback voltage FB in the DC-DC converter 3 becomes high in accordance with the size of the load Po. When the feedback voltage FB is higher than the second threshold voltage Vref2, the flip-flop 7a is reset so that electric charge stored in the capacitor Ct of the delay circuit 7d is discharged. When the charged voltage Vd of the capacitor Ct is lower than the reference voltage Vth1 after the passage of a predetermined time Td-on, the flip-flop 7e is set so that the operation-enable signal EN turns to [H]. As a result, operation of the power factor correction converter 2 is enabled so that working of the power factor correction converter 2 is restarted.
In a state where operation of the power factor correction converter 2 is stopped, the DC voltage Vb obtained by the output capacitor C2 of the power factor correction converter 2 changes periodically with a change width determined based on the size of the load Po and the capacitance of the output capacitor C1 as described above. Therefore, because attention has been heretofore entirely paid to the fact that a bottom voltage Vb-min of the DC voltage Vb changes dependently on the size of the load Po, the second threshold voltage Vref2 to be compared with the feedback voltage FB has been set based on the minimum value (bottom voltage Vb-min) of the DC voltage Vb.
However, when the AC voltage Vac is lower than a defined voltage (for example, 100 V) or when the capacitance of the output capacitor C1 is low, the feedback voltage FB increases as the aforementioned DC voltage Vb decreases even if there is no change in the size of the load Po. Then, there may arise a situation that the feedback voltage FB exceeds the second threshold voltage Vref2 set based on the minimum value (bottom voltage Vb-min) of the DC voltage Vb as described above and this situation may be detected as an increase of the load Po by mistake. For this reason, there is a problem that the increase of the feedback voltage FB caused by the increase of the load Po cannot be detected reliably.
As shown in FIG. 9, for explaining the relation between the feedback voltage FB and the DC voltage Vb depending on the AC voltage Vac when, for example, the load Po is 30 W (fixed), the feedback voltage FB increases as the DC voltage Vb decreases. When, for example, the output voltage Vb decreases to be not higher than about 85 Vdc, the feedback voltage FB always exceeds the second threshold voltage Vref2 set as described above though the load Po is fixed to a light load state as shown in FIG. 9.
Then, the comparator 7c detects this state, resets the flip-flop 7a, and sets the flip-flop 7e as described above, so that the operation-enable signal EN turns to [H]. As a result, the power factor correction converter 2 shifts to an operating state in accordance with the operation-enable signal EN even if there is no change in the size of the load Po. In other words, when the DC voltage Vb decreases with the decrease of the AC voltage Vac, there arises such a disadvantage that it is impossible to make the originally intended control in such a manner that the increase of the load Po is detected in an operation-stopped state of the power factor correction converter 2 to thereby restart operation of the power factor correction converter 2. Thus, as described above, there is a need in the art for an improved switching power supply device.